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MC13180PP/D Rev. 2, 08/2002 2.4 GHz Low Power Wireless Transceiver IC for BluetoothTM Applications
MC13180
Package Information Plastic Package Case 1314 (QFN-48) Ordering Information
Device PC13180FC Marking PC13180FC Package QFN-48
The MC13180 2.4 GHz Low Power Wireless Transceiver for BluetoothTM is a part of the comprehensive Bluetooth platform from Motorola that provides a complete, low-power Bluetooth Radio System for Bluetooth Class 1 or 2 power systems. The design is based on Motorola's third-generation Bluetooth architecture that has set the industry standard for interoperability, complete functionality, and compliance with the Bluetooth specification. When combined with a specified Motorola baseband controller such as the MC71000 or MC9328MX1, a complete Bluetooth solution can be realized. The MC13180 provides a unique combination of sensitivity, excellent C/I performance, and low power consumption. These performance parameters are extremely important to maintaining a robust link in high RF interference environments such as mobile phones, high density Bluetooth networks, 802.11b networks, microwave ovens, etc. * * * * * * * * * * Power Supply Range: 2.5 to 3.1 V Low Current Drain in Transmit (27 mA Peak) or Receive (37 mA Peak) Mode Minimum External Components Low IF Receiver with On-Chip Filters Fully Integrated Demodulator with A/D Direct Launch Transmitter Multi-Accumulator, Dual-Port, Fractional-N Synthesizer RSSI with A/D Bluetooth Class I Compatible Crystal Independent (12 to 15 MHz) Reference Oscillator or 12 to 26 MHz if supplied externally
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2002. All rights reserved.
Antenna
T/R Switch LNA 24 MHz
External T/R Enable Printed Balun Ramp Generator External PA Enable
Rx/Tx Enable LPA 45 Phase Splitter 45 High/Low Side Image Reject Mixer Programmable GFSK LUT PA Enable 2.5 GHz VCO CP/ LPF 3 - Acc Dual-Port, Frac-N Synthesizer Integer-N Synthesizer Internal Clocks Dividers 24 MHz CP/ LPF LPF Reference Oscillator 90 Phase Splitter Limiter
6-Bit, 4x Oversample A/D
Demod PMA BPF A/D RSSI
Rx/Tx Data
Rx/Tx Control Functions
Reset 2 ControlBus
External PA Control
Internal Memory
3
Interface Bus Rx/Tx Data Clock
D/A
LPF VCC
This device contains 81,604 active transistors.
Xtal
Figure 1. Simplified Block Diagram
2
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MOTOROLA
VCCMOD
GNDMOD
GNDVCO
VCCVCO
GNDPRE
VCCLNA
GNDMIX
VCCMIX
VCCPRE
GNDCP
48
VCC GNDLNA
47
46
VCC
45
VCC
44
43
42
VCC
41
40
VCC LPF
39
MLPF
38
37
VCC
1
LNA
High/Low IR Mixer
VCCCP
36 VSS
VDD
RFIN
2
T/R PMA LC VCC PA Buff PA SPI H/L Select from SPI
Main VCO D/A CP
35 VDD 34 VDDINT
GNDLNA
3 4
EPAEN
PRE
Frac-N
33 RES
VCCPA
5
LUT
32 CE
SPI
BPF
PA+
6 7
Ramp Generator
31 SDATA
GNDPA
30 SCK
Limiter
RSSI A/D SPI
PA-
8
29 CLK
Logic Core(LC)
GPO
9
D/A
LC
28 FS 27 RFDATA
Demod
EPADAC 10
SPI
DC PLL/VCO A/D LC
TIN+ 11 Test MUX TIN- 12 VCC
26 RTXEN
VCC
25 VCCDC
VCC Ref Osc
13
TOUT+
14
TOUT-
15
GNDLIM
16
VCCLIM
17
GNDDEM
18
VCCDEM
19
GNDX
20
BASE
21
EMM
22
COLL
23
DCVCO
24
DCCP
Figure 2. Device Pinout
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3
Electrical Characteristics
1 Electrical Characteristics
Table 1. Maximum Ratings
Ratings Supply Voltage VCCRF VDDINT Junction Temperature Storage Temperature Range TJ Tstg Symbol Value Unit V 3.2 3.2 150 -60 to 150 C C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Recommended Operating Conditions and Electrical Characteristics tables. 2. Meets Human Body Model (HBM) 2.0 kV and Machine Model (MM) 200 V except RF & I/O Pins = 50 V MM, RF Pins = 100 V HBM, and I/O Pins <500 V. RF pins have no ESD protection. Additional ESD data available upon request.
Table 2. Recommended Operating Conditions
Characteristic Power Supply Voltage Power Supply Voltage, Logic Interface (VDDINT VCCRF) Input Frequency Ambient Temperature Range Ref Osc Frequency Range (only integral multiples of 20 kHz may be used) With Crystal External Source Symbol VCCRF VDDINT fin TA fref 12 12 13 15 26 Min 2.5 1.65 Typ 2.7 Max 3.1 VCCRF 2.5 85 Unit Vdc Vdc
2.4 -20
25
GHz C MHz
Table 3. Digital DC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to
specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Supply Current CE, SDATA, SCK, RFDATA, RTXEN, Vin = 0 V or 1.8 V RES, Vin = 0 V (Reset Mode) RES, Vin = 1.8 V (Idle Mode) Radio Power Supply Current, Sleep Mode Radio Power Supply Current, Idle Mode Symbol ICCINT Min Typ Max Unit
ICCRFsleep ICCRFidle -
0.2 0.5 2.0 3.4
2.0 3.0 10 4.0
A mA A mA
4
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Electrical Characteristics Table 3. Digital DC Electrical Specifications (Continued)
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to
specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Radio Power Supply Current Transmit, 1 Slot Transmit, 3 Slot Transmit, 5 Slot Transmit, Continuous Radio Power Supply Current Receive, 1 Slot Receive, 3 Slot Receive, 5 Slot Receive, Continuous Output Voltage Low SDATA, CLK, FS, RFDATA ILoad = 0 A ILoad = 100 A Symbol Min Typ Max Unit mA ICCRFtx1 ICCRFtx3 ICCRFtx5 ICCRFtxc 22 25 26 27 33 mA ICCRFrx1 ICCRFrx3 ICCRFrx5 ICCRFrxc VOL 20 0.2 x VDDINT mV V 30 34 35 37 47.5
Output Voltage High SDATA, CLK, FS, RFDATA ILoad = 0 A ILoad = 100 A
VOH 0.8 x VDDINT VOL 20 0.2 x VCCRF 1.78 -
V
Output Voltage Low EPAEN, GPO ILoad = 0 A ILoad = 100 A
mV V
Output Voltage High EPAEN, GPO ILoad = 0 A ILoad = 100 A
VOH 0.8 x VCCRF VIL 2.68 -
V
Input Voltage Low RES, CE, SDATA, SCK, RFDATA, RTXEN Input Voltage High RES, CE, SDATA, SCK, RFDATA, RTXEN Input Current RES, CE, SDATA, SCK, RFDATA, RTXEN, Vin = 0 V or 1.8 V
0
0.3 x VDDINT -
V
VIH
0.7 x VDDINT -
VDDINT
V
Iin
1.0
-
A
MOTOROLA
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5
Electrical Characteristics Table 4. EPA DAC Electrical Specifications
(VCCRF = 3.1 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4 except R11/7 = 1, unless otherwise noted.) Characteristic Output Voltage EPADAC, ILoad = 100 A PADAC = 000000 PADAC = 100000 PADAC = 111111 Resolution Linearity Average Supply Current (1-slot packet) Symbol Vout 2.5 RESOL INL/DNL ICCDAC 0.02 1.60 3.08 6 1.0 197 0.4 2.0 500 Bits LSB A Min Typ Max Unit V
Table 5. Digital AC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults in Figure 4, unless otherwise noted. See Figure 3 Test Circuit and Figure 12 Timing Diagram.) Characteristic Propagation Delay, RTXEN to FS, receive mode Receiver Latency, LNA In to RFDATA, receive mode Receive Disable Time Strobe Delay, RTXEN to RFDATA, transmit mode Symbol TpropFS RXLAT TRXDIS Tstb TXsync Thold TXLAT TBit TTXDIS Min Typ 168 1.0 0 TXsync + 0.5 184 4.0 TXsync + 2.5 1.0 Max Unit s s s s s s s s s %
Transmit Sync Delay (i.e., R8/15-8) Hold Time, RTXEN to RFDATA, transmit mode Transmit Latency, RTXEN to PAout, transmit mode
182 -
192 -
Transmit Data Rate, Bit transfer rate to RFDATA, transmit mode Transmit Disable Time CLK Duty Cycle
-
-
30
20 40/60
70
6
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Electrical Characteristics Table 6. Receiver AC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Desired RFin = 2.441 GHz @ fdev = 157.5 kHz, Interferer fdev = 160 kHz, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Modulating data for desired signal = PRBS9, Modulating data for interfering signal = PRBS15, Measured BER < 0.1%, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = 25C, unless otherwise noted. Measurements made from LNAin to Recovered Data out. See Figure 3 Test Circuit.) Characteristics Receiver Sensitivity TA = 25C TA = -20 to 85C Receiver Sensitivity degradation in the presence of a dirty transmitter Maximum Usable Signal Level Co-Channel Interference @ -60 dBm Adjacent Channel Interference Adjacent (1 MHz) Interference @ -60 dBm Adjacent (2 MHz) Interference @ -60 dBm Adjacent (3 MHz) Interference @ -67 dBm Image Frequency Interference @ -67 dBm Adjacent Interference to In-Band Image Frequency @ -67 dBm Spurious Response Frequencies Intermodulation Performance [Note 1] Receiver Spurious Emissions 30 MHz to 1.0 GHz 1.0 GHz to 12.75 GHz Receiver Blocking Performance (See Figure 29) [Note 2] 30 MHz to 2.0 GHz (1.999 GHz) 2.0 to 2.399 GHz (2.399 GHz) 2.498 to 3.0 GHz (2.498 GHz) 3.0 to 12.75 GHz (3.001 GHz) SENSmax C/I co Symbol SENSmin -85 -80 -1.5 -75 -20 11 0 -30 -40 -9.0 -20 5 -39 -57 -47 dBm -25 -27 -27 -10 -9.0 -16 -16 2.0 -10 -27 -27 -10 dBm dBm -70 -56 -57 -47 dB -70 dB Min Typ Max Bluetooth Specs Unit dBm
-20 -
>0 8.0
11
dBm dB dB
C/I 1MHz C/I 2MHz C/I 3MHz C/I image
-
-8.0 -33 -46
0 -30 -40
-
-17
-9.0
C/I image 1
-
-33
-20
dB
-39
2 -31
5 -
NOTE: 1. Measured at f2 - f1 = 5.0 MHz in accordance to Bluetooth specification. 2. As allowed by the Bluetooth Specification, up to 5 exceptions may be taken for spurious response.
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7
Electrical Characteristics Table 6. Receiver AC Electrical Specifications (Continued)
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Desired RFin = 2.441 GHz @ fdev = 157.5 kHz, Interferer fdev = 160 kHz, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Modulating data for desired signal = PRBS9, Modulating data for interfering signal = PRBS15, Measured BER < 0.1%, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = 25C, unless otherwise noted. Measurements made from LNAin to Recovered Data out. See Figure 3 Test Circuit.) Characteristics RSSI Conversion Value, (R4/6 and R9/8 = 1) RF level at LNA input to maintain conversion value of: 1000 1111 RSSI Resolution (R4/6 and R9/8 = 1) RSSI Dynamic Range RSSI Average Supply Current (R4/6 and R9/8 = 1) Symbol RSSI Min Typ Max Bluetooth Specs Unit dBm
-60 RSSIres 20 -
-56 -70 1.8 40
-52 -66 dB/bit dB A
Table 7. Transmitter AC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Characteristics RF Transmit Output Power TA = 25C TA = 85C TA = -20C -20 dBc Occupied Bandwidth In-Band Spurious Emissions Adjacent Channel 2.0 MHz Offset Adjacent Channel 3.0 MHz Offset Adjacent Channel 3.0 MHz Offset In Band Spurious Emission Exceptions Out of Band Spurious Emissions 30 MHz to 1.0 GHz 1.0 to 12.75 GHz (2nd Harmonic) 1.8 to 1.9 GHz 5.15 to 5.3 GHz Peak Frequency Deviation Minimum Frequency Deviation High vs Low Frequency Modulation Percentage Initial Frequency Accuracy Symbol Pout -3.5 -3.5 -3.5 OccBW 1.9 0.1 2.4 930 4.0 4.0 4.0 1000 -6.0 to 4.0 -6.0 to 4.0 -6.0 to 4.0 1000 -20 -40 -40 3 dBm Outb1 Outb2 Outb3 Outb4 Dev DevMin ModIn 140 11.5 80 -57 -19 -58 -56 157.5 148 93 -36 -5.0 -47 -47 175 -36 -30 -47 -47 140 to 175 115 80 75 kHz kHz % kHz dBm Inb2 Inb3 Inbg3 Inbex -59 -65 -70 0 -20 -40 -40 3 Min Typ Max Bluetooth Specs Unit dBm
InitFA
-75
5.0
-75
kHz
8
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Electrical Characteristics Table 7. Transmitter AC Electrical Specifications (Continued)
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Characteristics Transmitter Center Frequency Drift One-slot packet Three-slot packet Five-slot packet Maximum Frequency Drift Symbol Min Typ Max Bluetooth Specs Unit kHz d1 d3 d5 Dmax -25 -40 -40 3.0 6.0 6.0 3.0 25 40 40 20 25 40 40 20 kHz/ 50 s dB
PA Output Impedance
S22
See Table 23
Table 8. Receiver AC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Modulation = GFSK, BT = 0.5, Bit Rate = 1.0 Mbps, Reference Crystal = 13 MHz, Register bit settings according to Figure 4, TA = -20 to 85C, unless otherwise noted. Measurements made at PAout. See Figure 3 Test Circuit.) Characteristic Maximum Usable Signal Level, TA = -20 to 85C Receiver Blocking Performance, TA = 25C W-CDMA 1.8 GHz W-CDMA 2.2 GHz GSM 1.8 GHz Co-Channel Interference @ -60 dBm, TA = -20 to 85C Adjacent Interference, TA = 25C Adjacent (1 MHz) Interference @ -70 dBm Adjacent (2 MHz) Interference @ -70 dBm Adjacent (3 MHz) Interference @ -77 dBm Image Frequency Interference @ -77 dBm, TA = 25C Adjacent Interference to In-Band Image Frequency @ -77 dBm, TA = 25C LNA Input Impedance C/I co Symbol SENSmax Min Typ 0 -14 -13 -13 8.0 Max Unit dBm dBm dB dB C/I 1MHz C/I 2MHz C/I 3MHz C/I image C/I image 1 S11 -8.0 -41 -47 -17 -33 dB dB
See Tables 20 and 21
dB
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9
Electrical Characteristics Table 9. MC7100/MC13180 Receive Characteristics
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted, interfering access code at the minimum Hamming distance of 14 according to Bluetooth specifications. See Figure 3 Test Circuit.) Characteristic False Detection Rate In Presence of Noise In Presence of Interfering Access Code @ Actual Sensitivity @ Actual Sensitivity + 10 dB Missed Detection Rate @ Actual Sensitivity @ Actual Sensitivity + 10 dB @ Actual Sensitivity - 16 dB Symbol Min Typ Max Unit % 0 0 0 % 0 0 100 -
Table 10. Reference Oscillator Receive Characteristics
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Crystal Frequency Range (SeeTable 19 for supported frequencies) External Drive Frequency Range (See Table 19 for supported frequencies) Oscillator Drive Level External Reference Crystal Reference Crystal Load Capacitance (Resonant Parallel) Maximum Crystal Equivalent Series Resistance (ESR) Typical Crystal Adjustment Range Recommended Crystal Tolerance over Temperature (-20 to 85C) Electronic Parallel Trim Capacitance Range Electronic Parallel Trim Capacitance Resolution Oscillator Bias Current (R11/0) = 0, (R11/4) = 0 or 1 (R11/0) = 1, (R11/4) = 0 (R11/0) = 1, (R11/4) = 1 Input Impedance at Base (Reference Frequency = 12 to 26 MHz, R11/0 = 0 or 1) Parallel Capacitance CPT Symbol fRefXtal fRefExternal Min 12 Typ Max 15 Unit MHz
12
-
26
MHz
Vpp 0.2 0.8 13 1.0 100 pF W
See Figure 19 10 ppm
-
0 to 9.3 0.3
-
pF pF A
-
0 50 200
-
CP
-
1.0 +
Parallel Trim Capacitance
-
pF
Parallel Resistance
RP
-
20
-
k
10
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Electrical Characteristics Table 10. Reference Oscillator Receive Characteristics (Continued)
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Input Bias Voltage (Base) Start-up Time (using Crystal) TWAIT Symbol Min Typ 1.2 7.5 Max Unit V ms
Table 11. Data Clock Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, Reference Crystal = 13 MHz, Register bit settings according to specified defaults, unless otherwise noted. See Figure 3 Test Circuit.) Characteristic Internal Reference Frequency Data Clock Output Frequency R Counter (R6/9-0) (Base 10) N Counter (R7/10-0) (Base 10) Loop Filter Bandwidth Phase Detector Gain Constant VCO Gain Constant Start-up Time External Reference Crystal Reference Kpd KVCO Symbol Min 3 3 Typ 20 24 650 1200 1.0 15.9 15 Max 4000 1023 2047 200 kHz A/rad MHz/V ms 1.0 7.5 Unit kHz MHz
Table 12. SPI AC Electrical Specifications
(VCCRF = 2.7 Vdc, VDDINT = 1.8 Vdc, TA = 25C, unless otherwise noted. See Figure 13 Timing Diagram.) Characteristic CE to SCK Setup Time Hold Time SDATA to SCK Setup Time Hold Time SCK to SDATA Propagation Delay SCK Operating Frequency (50% Duty Cycle) SPI Setup Time to RTXEN (See Figure 12) Symbol Min Typ Max Unit ns TsuCE THCE 20 20 ns TsuD THD Tprop fmax TSUSPI 20 20 20 20 20 ns MHz ns
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11
VccLNA
VccMIX VccMOD
VccPRE
VccCP
LNA In SMA Johnson 142-0701-881 U7 VCCLNA GNDMIX VCCMIX VCCMOD GNDMOD GNDVCO VCCVCO GNDPRE VCCPRE MLPF GNDCP VCCCP C37 1.0 48 47 46 45 44 43 42 41 40 39 38 37 L1 3.9n VddINT
R5
620
13 14 15 16 17 18 19 20 21 22 23 24
TOUT+ TOUTGNDLIM VCCLIM GNDDEM VCCDEM GNDX BASE EMM COLL DCVCO DCCP
12
C7 VccVC O 270p R4 27k TL6 C10 22p Vdd TL5 C4 3.3 p VSS VDD VDDINT RES CE JD/MSLE 620 VccPA
Electrical Characteristics
PA Out SMA Johnson 142-0701-881
R6
MC13180
Data CLK FS Data_IO VccDC Clock Recovered Clock Recovered Data
TL2
TL4
VccRF C11 1.5p (0.1 pF) TL1 TL3
C12 560p
C13 33p
1 2 3 4 5 6 7 8 9 10 11 12 GNDLNA RFIN GNDLNA EPAEN VCCPA PA+ GNDPA PAGPO EPADAC TIN+ TINSDATA SCK CLK FS RFDATA RTXEN VCCDC NRES NCEN SPID SPICK CLK FS RFDataIO RTXEN
36 35 34 33 32 31 30 29 28 27 26 25
Figure 3. Test Circuit
VccXTAL VccRF
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VccLIM VccDEMO C2 33n C5 22p 13 MHz NDK Y1 W-168-179 C8 12p
VccPRE VccVCO VccMIX VccMOD C22 100n C23 2.2n C24 6.8 p
VccXTAL VccDC C28 100n VccPA C31 100n
Printed Transmission Lines TL1 = 77 W, 9.9 @ 2.45 GHz TL2 = 77 , 9.9 @ 2.45 GHz TL3 = 77 , 10.5 @ 2.45 GHz TL4 = 77 , 10.5 @ 2.45 GHz TL5 = 50 TL6 = 50 TL7 = 50 TL8 = 50
VccLNA C18 6.8p
VccCP C26 100n
VccLIM VccDEMO C29 100n Vdd
Default Units: Microfarads, Microhenries and Ohms
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MC13180: Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Byte 1
Byte 0 LSB Bit 0
Register Address
Register Number
MSB Bit 15
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16 Bit Frac-N Numerator Divide Value - num 0 1 Tx Enable MSB 1 1 General Purpose Output Invert MSB 0 0 0 0 RSSI Read Enable 1 1 1 1 0 0 0 1 0 0 1 1 0 0 PA Bias Adjust 0 MSB 1 Dual Port Programmable Delay For Tx PLL MSB 1 Transmit Synchronization Time Delay Value LSB 0 RSSI Enable 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 0 MSB 1 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 Xtal Trim LSB MSB 1 0 1 0 0 0 1 0 1 DC Pll R Counter 0 DC Pll N Counter 1 1 0 B-Dual Port Digital Multiplier Value For Tx PLL 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 1 PA DAC Setting 0 0 Frac-N Integer Divide Valu 0 0 0 0 0 1 External PA Enable Invert 1 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 Rx Enable General Purpose Output 1 0 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 Narrow Bandwidth Enable 0 0 High/Low Injection Enable 1 0 0 0 0 0 1 0 1 1 1 1 1 1 External PA DAC Enable 1 ROM_r2_c2 1 ROM_r2_c4 1 ROM_r3_c2 1 ROM_r3_c4 0 ROM_r4_c3 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0 0 MSB 1 MSB 1 MSB 0 MSB 1 MSB 0 MSB 1 1 0 0 1 0 1 0 1 1 0 ROM_r4_c4 1 1 0 0 0 1 ROM_r4_c2 1 0 0 0 1 0 ROM_r3_c3 1 0 0 1 0 0 ROM_r3_c1 0 1 0 1 0 0 ROM_r2_c3 0 1 0 1 External PA Enable 1 1 1 1 Xtal Boost Enable 0 ROM_r1_c1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 M-Dual Port Digital Multiplier Value for Tx PLL 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
$00 Programmable Reset LSB
$01
1
MSB
Rx Test Tx Test
0 1
$02
2
Sleep Enable
LSB
Rx Test Tx Test
0 0
$03
3
LSB
0
$04
4
1
$05
5
0
$06
6
External PA Enable = GPO
LSB
1
$07
7
LSB
1
$08
8
MSB
LSB
1
$09
9
0
$0A
10
Figure 4. Register Map
0
MC13180 Product Preview
$0B
11
Xtal Enable
1
$0C
12
MSB
LSB
1
$0D
13
MSB
LSB
1
$0E
14
MSB
LSB
0
$0F
15
MSB
LSB
1
$10
16
MSB
LSB
1
$11
17
LSB
0
$12
18
Electrical Characteristics
0
13
14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB 0 0 0 0 0 0 LSB 0 0 0 0 MSB 0 0 1 1 0 0 LSB 0 0 0 0 MSB 0 0 0 0 0 0 0 0 0 0 0 0 0
Electrical Characteristics
$13
19
$14
20
$15
21
$16
22
$17
23
$18
24
$19
25
$1A
26
Figure 4 Register Map (continued)
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Bit 3:0 of Part Number
1 1 MSB 0 0 1
$1B
27
$1C
28 Read Only
$1D
29 Read Only
RSSI Conversion
0
LSB 0
$1E
30 Read Only
Manuf. ID (continuation code)
Manuf. ID (non-continuation code)
1 1 1
LSB 0
1 1
$1F
31 Read Only Version Number
Bit 15:4 of Part Number
1 1 0 1 1 1
MOTOROLA
Pin Connections
2 Pin Connections
Table 13. Pin Function Description
Pin 1 Symbol/ Type GNDLNA Equivalent Internal Circuit Description GNDLNA, Negative supply GNDLNA is the ground for the LNA.
1
2
RFIN
Bias
RF in
2
LNA output to balun
T/R 3
RFIN RFIN is the RF input to the LNA. The LNA is a bipolar cascode design. The input is the base of the common emitter transistor. Minimum external matching is required to optimize the input return loss and gain. The cascode output drives the primary of an on-chip balun single-ended. GNDLNA, Negative supply GNDLNA is the ground for the LNA. VCCLNA, Positive supply VCCLNA is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It is decoupled to GNDLNA at the pin of the IC.
3
GNDLNA
1.7 mA
48
VCCLNA
48 VCC 6.8 pF
4
EPAEN
4
VCC
VCC Sequence Manager Control or SPI Control
EPAEN External PA enable is a digital output which can be used to enable an external PA. It can be controlled via SPI or placed under sequence manager control. This output can also be used to control an external T/R switch requiring complementary drive.
NOTE:
VCC = VCCRF
MOTOROLA
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 5 Symbol/ Type VCCPA See Figure 5. Equivalent Internal Circuit Description VCCPA, Positive Supply VCCPA pin is taken to the incoming positive battery or regulated dc voltage through a low impedance trace on the PCB. It is decoupled to GNDPA at the pin of the IC. GNDPA, Negative Supply GNDPA pin is taken to an ample dc ground plane through a low impedance path. The path should be kept as short as possible. A multi-sided PCB is implemented so that ground returns can be easily made through via holes. PA + Positive differential PA output. An external differential-to-single-ended matching network is desired. PA Negative differential PA output. An external differential-to-single-ended matching network is desired.
VCC 9 VCC
7
GNDPA
6
PA+
8
PA -
9
GPO
SPI Control
GPO The General Purpose Output is a digital output. GPO can be controlled by the SPI. This signal can also be used to control an external T/R Switch. EPADAC External PA driver. Analog output ranges from 0.02 to VCCRF - 0.02. The EPADAC is linearly scaled to a maximum VCC of 3.1 V.
10
EPADAC
VCC 10
VCC SPI Control
NOTE:
VCC = VCCRF
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 11 Symbol/ Type TIN +
Inject/Monitor Decoder SPI RX/TX Chain
Equivalent Internal Circuit
Description TIN + This pin is for factory use only. It can be grounded or left open. TIN This pin is for factory use only. It can be grounded or left open. TOUT + This pin is for factory use only. It must be left open. TOUT This pin is for factory use only. It must be left open.
12
TIN 11
VCC
13
TOUT +
12
VCC
14
TOUT VCC 13
VCC 14
15
GNDLIM
15
VCC
GNDLIM, Negative supply GNDLIM is the ground for limiter. VCCLIM, Positive supply VCCLIM is decoupled to GNDLIM at the pin of the IC. GNDDEM, Negative supply GNDDEM is the ground for demodulator. VCCDEM, Positive supply VCCDEM is decoupled to GNDDEM at the pin of the IC.
100 nF 16
16
VCCLIM
17
GNDDEM
17
VCC
100 nF 18
18
VCCDEM
NOTE:
VCC = VCCRF
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 19 Symbol/ Type GNDX Equivalent Internal Circuit Description GNDX Reference oscillator ground. BASE Reference oscillator base. The base is the reference oscillator input. An on-chip capacitor trim network is also included to allow the user to use relatively inexpensive crystals. EMM Reference oscillator emitter. A bias current of 50 A is supplied internally to the emitter. COLL Reference oscillator collector. The collector is tied to VCC. The pin of the IC is bypassed to gnd. DCVCO Data Clock Loop Filter VCO control voltage. This pin can be used to raise/lower the loop corner frequency in conjunction with the DCCP pin and external components. DCCP Data Clock Loop Filter charge pump. VCCDC Data clock VCC. The pin of the IC is bypassed to gnd. RTXEN When RTXEN is asserted (high), it controls the start of the Rx or Tx cycle. Digital input. The logic level is internally shifted to the VDD supply.
20
BASE
19 100 nF VCC 22
1.6 V 13 MHz 20 22 pF 12 pF 21 Bias Current
10 mA
21
EMM
50 k Trim CPT
22
COLL
Shown for 13 MHz reference oscillator.
23
DCVCO
VCC 23 VCC 24 33 nF 9.0 k VCC VCC 100 nF 25 Charge Pump DC VCO Control Voltage
24
DCCP
25
VCCDC
26
RTXEN
VDDINT VDDINT
26
NOTE:
VCC = VCCRF
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 27 Symbol/ Type RFDATA
VDDINT
Equivalent Internal Circuit
Description RFDATA This digital I/O is used for Transmit Data (input) and Received Data (output). When in transmit mode, the logic level is internally shifted to the VDD supply.
VDDINT
27
VDDINT
28
FS
VDDINT
VDDINT
28
FS Frame-sync digital output (used for Rx only). In Receive mode, this signal brackets a 6-bit sample frame.
29
CLK
VDDINT
VDDINT
29
CLK Clock associated with RF data path. The Clock Frequency must always be programmed to 24 MHz. Digital output.
30
SCK
VDDINT VDDINT
SCK SPI clock.
30
NOTE:
VCC = VCCRF
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 31 Symbol/ Type SDATA
VDDINT
Equivalent Internal Circuit
Description SDATA SPI data. Digital input or output. As an input, the logic level is internally shifted to VDD.
VDDINT
31
VDDINT
32
CE
VDDINT VDDINT
32
CE Chip enable is active low enable to facilitate SPI transfers. Digital input. The logic level is internally shifted to the VDD supply.
33
RES
VDDINT VDDINT
33
RES Asynchronous Digital Reset (Active Low). Resets MC13180 register settings to a default value. Digital Input. The logic level is internally shifted to the VDD supply.
34
VDDINT
34 I.0 mF
VDDINT Digital interface supply voltage. 1.65 V VDDINT 3.1 V. VDDINT must, at all times, be VCC.
35
VDD
VCC 1 F 35 36
VDD Digital core supply. The pin of the IC is bypassed to gnd. Logic Levels are internally shifted from VDDINT to/from VDD. VSS Digital ground.
36
VSS
NOTE:
VCC = VCCRF
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Pin Connections Table 13. Pin Function Description (Continued)
Pin 38 Symbol/ Type GNDCP
38
Equivalent Internal Circuit
Description GNDCP Main frac-N charge pump ground. VCCCP Main frac-N charge pump VCC. It is decoupled to GNDCP at the pin of the IC.
37
VCCCP
V CC
100 nF
37 3.5 pF To VCO
39
MLPF
27 k* 270 pF* * values shown for 13 MHz reference 39
V CC
10 pF
30 k
50 k
MLPF Main frac-N loop filter (Charge Pump). The filter is referenced to VCC. GNDPRE Prescaler ground. VCCPRE Prescaler VCC. The pin of the IC is bypassed to GNDPRE. VCCVCO VCCVCO is decoupled to GNDVCO at the pin of the IC. Extreme caution should be used when decoupling/routing to this pin. GNDVCO VCO ground. GNDMOD Modulation DAC ground. VCCMOD Modulation DAC VCC. The pin of the IC is bypassed to GNDMOD. GNDMIX Mixer ground. VCCMIX Mixer VCC. The pin of the IC is bypassed to GNDMIX.
41
GNDPRE
41
VCC
100 nF 40
40
VCCPRE
42
VCCVCO
VCC 42 6.8 pF 100 nF 43
43
GNDVCO
44
GNDMOD
44
VCC
100 nF 45
45
VCCMOD
47
GNDMIX
47
VCC
100 nF 46
46
VCCMIX
NOTE:
VCC = VCCRF
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Pin Connections
VCC
5
100 nF 7 TL5 VCC 560 pF 33 pF 3.3 pF
620 TL2
TL4
6
1.5 pF (0.1 pF) TL1 620 TL3 8
PAin-
PAin+
(Adjustable Current Source) Vref
Figure 5. Equivalent Internal Circuit for Pins 5, 6, 7, and 8
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Typical DC Performance Characteristics
3 Typical DC Performance Characteristics
ICCINT, LOGIC INTERFACE CURRENT (A)
900 850 800 750 700 650 600 550 500 1.8 2.0 2.2 2.4 2.6 2.8 VDDINT, LOGIC INTERFACE VOLTAGE (V) 3.0 TA = 25C
ICCRFtxc, CONTINUOUS TRANSMIT CURRENT (mA)
28.5 28 27.5 27 26.5 26 25.5 25 2.4
TA = 25C
2.5
2.6
2.7
2.8
2.9
3.0
3.1
VCCRF, POWER SUPPLY (V)
Figure 6. Logic Interface Current versus Logic Interface Voltage (Idle Mode)
ICCRFtxc,CONTINUOUS TRANSMIT CURRENT (mA)
Figure 7. Continuous Transmit Current versus Power Supply
ICCRFrxc, CONTINUOUS RECEIVE CURRENT (mA)
39 38.5 38 37.5 37 36.5 36 35.5 35 34.5 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 TA = 25C
29
28
VCCRF = 2.7 V
27
26
25 -20
-5.0
10
25
40
55
70
85
TEMPERATURE (C)
VCCRF, POWER SUPPLY (V)
Figure 8. Continuous Transmit Current versus Temperature
ICCRFrxc, CONTINUOUS RECEIVE CURRENT (mA)
Figure 9. Continuous Receive Current versus Power Supply
39
38
VCCRF = 2.7 V
37
36
35 -20
-5.0
10
25
40
55
70
85
TEMPERATURE (C)
Figure 10. Continuous Receive Current versus Temperature
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Functional Description
4 Functional Description
Note: In the following description, control bits contained in the MC13180 register map for various functions will be identified by register number and bit number(s). For example, bit R4/8 references bit 8 of register 4 while R5/9-3 identifies bits 9 through 3, inclusive, of register 5 (decimal notation). Unless otherwise noted, a default register map configuration as listed in Figure 4 is assumed.
4.1 Overview
The MC13180 is a complete RF transceiver for Bluetooth applications. The device, when coupled with an MC71000 controller or any controller containing an integrated Joint Detection/Minimum Length Sequence Estimator (JD/MLSE) digital decoder, exhibits superior RF performance with small size and low cost. Only minimal external components are required to complete the RF link of a Bluetooth system.
4.2 MC13180 States
Figure 11 illustrates the various states which the MC13180 can assume. A description of each state follows.
4.3 OFF State
In the OFF state, no power is being applied to the VCCRF or VDDINT of the device. During this state, all digital inputs should be held at ground to avoid forward biasing internal ESD diodes.
4.4 POWER UP State
During this state, power is applied to the device in an orderly fashion. All digital inputs should continue to be held at ground. Since VDDINT of the device must always be less than or equal to the VCCRF supplied to the device, it is generally desired to first allow the VCCRF to rise and stabilize, then follow with applying the VDDINT supply. This prevents internal protection diodes from forward biasing. SPI operations are not allowed during this state.
4.5 RESET State
The RESET state can be entered at any time from any state with the exception of the OFF and POWER UP states. During the RESET state, SPI operations are forbidden. The RESET state places the entire contents of the internal register map into a known condition. All digital outputs are active and driven to a logic low. The SDATA I/O pin is configured as an input, and the RFDATA I/O pin is configured as an output. The crystal oscillator is inactive and therefore the CLK output remains at a static low level.
4.6 CONFIG State
Once the RES pin is de-asserted, the crystal oscillator and data clock PLL of the device become active. The CLK output will attempt to synthesize a clock frequency based upon the crystal oscillator frequency and values loaded into the data clock N and R registers. These values assume an initial reference frequency of 13 MHz and the data clock values are initialized from reset to synthesize 24 MHz from this reference.
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Functional Description
During the Config state, any address location can be read or written. The Sleep Enable, Tx Enable, and Rx Enable bits of the register map must remain at a logic zero, otherwise the register map is typically loaded with user defined default values.
4.7 WAIT XTAL State
During this state, the crystal oscillator and data clock PLL are stabilizing. If an external reference oscillator is being used, the data clock PLL must still be allowed to settle. Stability will be achieved after TWAIT, at which time the Idle state is entered.
4.8 IDLE State
In the Idle state, the CLK output supplies a synthesized 24 MHz output. Any SPI operation is allowed during this state. RSSI information is typically read during the Idle state.
4.9 TX CONFIG State
During this state, the contents of the register map are set for any desired transmit information, including the transmit channel setting. The Tx Enable (R2/14) bit of the register map is also asserted which places the RFDATA pin into the input state at the completion of the SPI write cycle.
4.10 TX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state.
4.11 TX MODE
Data presented to the RFDATA pin is transmitted to the PA output of the device. SPI operations are forbidden during this state. The TX mode is ended by de-asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until TTXDIS s after the RTXEN pin is de-asserted.
4.12 RX CONFIG State
During this state, the contents of the register map are set for any desired receive information, including the receive channel setting. The Rx Enable (R2/13) bit of the register map is also asserted which places the RFDATA pin into the output state at the completion of the SPI write cycle.
4.13 RX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state.
4.14 RX MODE
Digitized and oversampled data from the desired receive channel is presented to the RFDATA pin and framed by the FS signal. Data is aligned to the rising edge of the CLK output. SPI operations are forbidden during this state. The RX mode is ended by de-asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until TRXDIS s after the RTXEN pin is de-asserted.
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Functional Description
4.15 SLEEP State
The Sleep state is entered by asserting the Sleep Enable (R2/15) bit of the address map. During this mode, the CLK pin is driven to a static logic low level, and the crystal oscillator is disabled. All digital outputs are driven to a logic low level. SPI operations are permitted during this state. The Idle state is entered by de-asserting the Sleep Enable bit of the address map.
OFF VCCRF = 0 V VDDINT = 0 V
Power Up 2.5 V VCCRF 3.1 V 1.65 V VDDINT VCCRF RES = 0 Reset RES = 1 Configure "SPI Load" Sleep Sleep EN (R2/15) = 0 Wait XTAL Sleep EN (R2/15) = 1 * Can be entered from any State
Wait XTAL
Idle TX Enable (R2/14) = 0 RX Enable (R2/13) = 0
TX Enable (R2/14) = 1 TX Configure RTXEN = 1 RTXEN = 0 TX Warm Up
RX Enable (R2/13) = 1 RX Configure RTXEN = 1 RX Warm Up RTXEN = 0
TX Mode
RX Mode
Figure 11. State Diagram
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Functional Description
4.16 Receive Data Path
The MC13180 is placed into the receive mode from the idle mode by asserting the RTXEN pin after setting the Receive Enable bit (R2/13), clearing the Transmit Enable bit (R2/14), and clearing the Narrow Bandwidth Enable bit (R2/12) (See Figure 12). The RFDATA pin of the device is configured as an output as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the receive mode are shown in Table 14. The interface signal levels are internally translated to/from VDDINT to VDD. To initiate a receive cycle, the user will set the local oscillator frequency of the device in conjunction with the High/Low Injection Enable bit. Optionally, other address map values may be written or read. During this "SPI" cycle, the device's RTXEN must be de-asserted. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the receive mode. Serialized, A/D data will appear at the RFDATA pin, framed by the FS pin, after TpropFS. The data represents a 6-Bit, 2's-complement digital value and is sampled four times for every data bit. Once the receive cycle is complete, the RTXEN pin is de-asserted and the MC13180 begins an internal power down sequence.
4.17 Transmit Data Path
The MC13180 is placed into the transmit mode from the idle mode by setting the Transmit Enable bit (R2/ 14), setting the Narrow Bandwidth Enable bit (R2/12), and clearing the Receive Enable bit (R2/13) of the address map, then asserting the RTXEN pin of the device (see Figure 12). The RFDATA pin of the device is configured as an input as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the transmit mode are shown in Table 14. The interface signal levels are internally translated to/from VDDINT to VDD. To initiate a transmit cycle, the user will normally set the desired channel frequency and mode bits mentioned above. Optionally, other address map values may be written or read. During this "SPI" cycle, the device's RTXEN must be de-asserted, ensuring that the device remains in idle mode. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the transmit mode. Data to be transmitted must be set and stable no later than Tstb after the assertion of RTXEN. The RF data will be present at the PA output after RTXEN time, TXLAT. Subsequent serial data can then continue to be presented to the MC13180 via the RFDATA pin, and the CLK of the device (divided by 24) can be used as the system clock to synchronize the data transfer. Once the data stream has been transmitted and the time Thold is met, the RTXEN pin is de-asserted and the MC13180 begins an internal power down sequence. Since RF power is still present at the PA output, no SPI operations or additional cycles can be performed for at least TTXDIS s. At this time, RF power is at a substantially low enough level as to not produce undesired emissions.
4.18 Transmit Synchronization Delay
A programmable delay exists between the rising edge of RTXEN and the first available bit of data. This delay range is TXsync and is set via SPI bits of Transmit Synchronization Time Delay Value (R8/15-8) where the value represents the delay in microseconds. Packet data is seen at the antenna approximately 2.5 s after this delay. Refer to Figure 12 for the corresponding timing diagram. All Bluetooth packets require a minimum of four preamble bits of pattern 0101 or 1010. For minimum power consumption, set the delay to TXsync minimum. If additional settling time or preamble bits are required, manipulate the delay as necessary, up to TXsync maximum.
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Functional Description
4.19 Main Loop Bandwidth
During a transmit cycle, Narrow Bandwidth Enable (R2/12) must be set to a logic one. During a receive cycle this bit must be set to a logic zero. Changing the loop bandwidth of the Main Loop Filter in this manner maximizes radio performance. Note that this bit is externally gated by the sequence manager.
Table 14. Data Direction and Signal Description for the MC13180 Baseband Interface
Pin Name RFDATA FS RTXEN CLK RX Direction MC13180 Baseband MC13180 Baseband MC13180 Baseband MC13180 Baseband RX Mode Description RX data Start of each 6-bit sample Receive mode enable Data sample clock
Pin Name RFDATA FS RTXEN CLK
TX Direction MC13180 Baseband MC13180 Baseband MC13180 Baseband MC13180 Baseband
TX Mode Description TX data Signal is unused and remains low Transmit mode enable Data sample clock
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TX Cycle TSUSPI TTXDIS Tstb 1 2 3 12 ... ... ... ... 12 ... 22 23 24 2 1 3 22 23 24 ...... D0 TBIT Dn THOLD Valid RF TXLAT D1 RX Cycle TSUSPI TRXDIS TpropFS 1 2 5 1 4 6 ... 3 2 3 4 5 6 1 2 ... ... D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 D5 D4 RXLAT Valid RF ... ... ......
SPI
VDDINT GND VDDINT GND VDDINT GND VDDINT GND
RTXEN
CLK
RFDATA
PA OUT
Figure 12. TX and RX Cycle Timing
MC13180 Product Preview
SPI
VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT GND
RTXEN
CLK
FS
RFDATA
LNA IN
Functional Description
29
Functional Description
4.20 Serial Peripheral Interface (SPI)
Basic functionality of the MC13180 is controlled by configuring the internal address map of the device (see Figure 4). The address map is completely read/writable and is organized as 32 addresses of 2-bytes (16-bits) each. The serial interface to this map is controlled by the CE, SDATA, and SCK pins. In addition, the entire address map can be placed into a known state by either asserting the RES pin or by writing to address zero of the device. Logic interface levels are controlled by the VDDINT pin. The interface signal levels are internally translated to/from VDDINT to VDD. The non-standard SPI uses a bi-directional SDATA pin to transfer information to/from the MC13180. Data is clocked into and out of the device on the rising edge of SCK (SCK is of RZ format). The CE pin enables the device SPI and transfers the contents of the SPI shift register to the decoded address when de-asserted. The MC13180 device address is defined to be 01 (binary). This scheme allows for up to three additional SPI devices to be cascaded together without requiring an additional chip enable line. Figure 13 shows a SPI write operation. SPI transfers begin with the assertion of the CE pin when RES is de-asserted. The first bit clocked into the SPI is the R/W bit which equals a logic zero to indicate a SPI write operation. The next two bits are the MC13180 device address (i.e., 01). The remaining five bits of the address field represent the target address to which information will be transferred. The data field proceeds the address field. Data is clocked into the SPI from MSB to LSB. Once the LSB has been entered, the CE pin is de-asserted and the data field contents are transferred to the MC13180's target address. A SPI write to address zero resets all register map values to their initial (reset) condition. Figure 13 also shows a SPI read operation. The first bit clocked into the SPI is now a logic one, indicating a read operation is desired. Again, the next two bits clocked into the SPI are 01, the MC13180 device address. The next five bits of the address field will be the target address to be read. On the falling edge of the SCK, the SDATA line becomes high impedance. This condition remains until the next rising edge of SCK, where data is driven onto the SDATA pin. Data should be sampled for reading on the falling edge of SCK. Once all data has been shifted out of the SPI, the CE pin is de-asserted and the SDATA line becomes an input to the MC13180. Again, reading from address zero will reset the entire register map values to their initial condition. Important Note: All SPI signals (CE, SCK, and SDATA) should remain completely static during an active receive or transmit cycle to prevent digital feedthrough to the RF portions of the chip. Failure to follow this condition can cause severe performance degradation.
SPI Write Operation RES CE T suCE R/W 0 1 A5 A4 THD A3 A2 A1 A0 D15 D14 D1 D0 THCE VDDINT 0V VDDINT 0V VDDINT 0V VDDINT 0V
SDATA SCK
0 0
TsuD SPI Read Operation RES CE R/W 0 1 A5 A4 A3 A2 A1 A0 Hi Z D15 D14 D1 D0 Hi Z VDDINT 0V VDDINT 0V VDDINT 0V VDDINT 0V
SDATA SCK
... ...
fmax
Tprop
Figure 13. SPI Register Map
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MOTOROLA
Functional Description
4.21 Crystal Oscillator
The crystal oscillator provides the reference for the data clock PLL and main PLL. It can be configured as a Colpitts type (negative resistance) oscillator and utilize an external parallel resonant crystal or may be driven from an external source. The oscillator circuit has an on-chip capacitor trim network that provides the capability to compensate for crystal and/or load capacitor tolerances. This allows the use of relatively inexpensive crystals with as much as 50 ppm tolerance. The oscillator also provides three bias current modes. Xtal Enable (R11/0) enables/disables the bias current and Xtal Boost Enable (R11/4) enables/ disables a high current mode. Refer to the Reference Oscillator Electrical Characteristics for the available current modes. Table 15 gives examples of parallel trim capacitances that can be programmed to register map location Xtal Trim (R6/14-10). Typical stray capacitance is on the order of 1.0 pF. To drive the oscillator with an external source, program the Xtal Enable (R11/0) to zero and ac-couple the external signal into the oscillator base with a 15 to 100 pF capacitor. It is also recommended to set Xtal Trim (R6/14-10) to zero to reduce the load on the external source. Additional characteristic data is shown in Figures 14 through 19.
Table 15. Examples of Programmable XTAL Trim Capacitances
XTAL Trim (R6/14-10) Setting (MSB to left) 00000 00100 10000 10101 11111 Electronic Parallel Crystal Trim Capacitance (CPT) 0 pF 1.2 pF 4.8 pF 6.3 pF 9.3 pF
OSCILLATOR NEGATIVE RESISTANCE ()
16
OSCILLATOR OPEN LOOP GAIN (dB)
0 -50 -100 -150 -200 -250 25C -300 -350 0 4.0 8.0 12 16 20 24 28 32 ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10) See Figure 42, TA = 25C Curve Measured with 13 MHz Crystal Reference Crystal Load Capacitance Ratio = 1.8 (C5/C6) TA = -20C 85C
14 12 10 8.0 6.0 4.0
See Figure 42, TA = 25C Open Loop Gain Measurements @ -10 dBm Crystal Load Capacitance = 13 pF Electronic Trim (R6/14-10) = 16 (decimal)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CRYSTAL CAPACITOR RATIO (C5/C8)
Figure 14. Oscillator Open Loop Gain versus Capacitor Ratio
Figure 15. Oscillator Negative Resistance versus Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4) = 0
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Functional Description
OSCILLATOR NEGATIVE RESISTANCE ()
OSCILLATOR NEGATIVE RESISTANCE ()
0 -200 -400 -600 -800 -1000 -1200 -1400 0 85C 4.0 25C See Figure 42, TA = 25C Curve Measured with 13 MHz Crystal Reference Crystal Load Capacitance Ratio = 1.8 (C5/C6) TA = -20C
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 See Figure 42, TA = 25C Curve Measured with 13 MHz Crystal Reference Parallel Crystal Trim (R6/14-10) = 16 (decimal)
8.0
12
16
20
24
28
32
ELECTRONIC PARALLEL CRYSTAL TRIM (R6/14-10)
CAPACITOR RATIO (C5/C8)
Figure 16. Oscillator Negative Resistance versus Electronic Parallel Crystal Trim (CPT) (Crystal Boost Enable R11/4) = 1
11
Figure 17. Oscillator Negative Resistance versus Crystal Capacitor Ratio (Crystal Boost Enable R11/4) = 0
600
CRYSTAL FREQUENCY PULLING (Hz)
CRYSTAL START-UP TIME (ms)
10 9.0 8.0 7.0 6.0
See Figure 42, TA = 25C 13 MHz Crystal Reference
400 200 0 -200 -400 -600
See Figure 42, TA = 25C Crystal Frequency Delta measured relative to intial frequency for R/14-10 = 12 (decimal).
0
1.0
2.0
3.0
4.0
5.0
0
4.0
8.0
12
16
20
24
28
32
CAPACITOR RATIO (C5/C8)
ELECTRONIC PARALLEL TRIM VALUE (R6/14-10)
Figure 18. Crystal Start-up Time versus Capacitor Ratio
Figure 19. Crystal Frequency Pulling versus Electronic Parallel Trim Value
4.22 Data Clock Operation
The data clock phase lock loop is responsible for providing a constant 24 MHz reference for use throughout the device. The MC13180 uses a simple integer-N synthesizer to derive a 24 MHz clock (CLK) from the reference frequency. The counter values must always be set to the appropriate values to generate this 24 MHz clock frequency. The general model for the Phase Lock Loop (PLL) is illustrated in Figure 20. For the circuit in Figure 42, the external low pass filter has a loop filter bandwidth (LBW) of 1.0 kHz. This proves to be adequate for any value of external reference frequency that is an integral multiple of 20 kHz. More details about PLL loop filters can be obtained from Motorola application note AN1253/D. The R-counter of the synthesizer (R6/9-0) is set to a value which will set the internal reference frequency frefInternal to 20 kHz; thus R = frefExternal / 20 kHz. The N-counter of the synthesizer (R7/10-0) is set to multiply frefInternal to 24 MHz; thus N = 24 MHz / frefInternal. For the case of a 13 MHz external reference, R = 65010 and N =120010.
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Functional Description
For applications utilizing frefExternal > 20 MHz, the external low pass filter with a 1.0 kHz corner frequency is still usable. However, due to the R counter limitations, the R counter is programmed to generate the frefInternal to 40 kHz (recommended). For the case of a 26 MHz external reference, R = 65010 and N = 60010. The N and R counters can only divide by integer values and the greatest common divider must be found to represent frefInternal and achieve CLK. Table 16 provides the appropriate values for various frefExternals. For applications that require a faster data clock PLL response time, refer to the data clock electrical characteristics and Motorola application note AN1253/D. Additional data clock characteristic data is shown in Figures 21 and 22.
Table 16. Data Clock R and N Counter Values for 20 kHz frefInternal with 1.0 kHz LBW
frefExternal (MHz) 12 13 14.4 16.8 19.22 19.68 19.88 26 frefInternal (kHz) 20 20 20 20 20 20 20 40 R Counter (Decimal) 600 650 720 840 961 984 994 650 N Counter (Decimal) 1200 1200 1200 1200 1200 1200 1200 600 LBW (kHz) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.4
frefExternal
/R
frefInternal
Phase Detector (Kpd)
Filter (Kf)
VCO (KVCO)
fo
Divider (Kn)
Figure 20. General Model for the PLL
Where: Kpd = Phase Detector Gain Constant Kf = Loop filter transfer function KVCO = VCO Gain Constant Kn = Divide Ratio (1/N) frefInternal = Input Frequency fo = Output frequency fo/N = Feedback frequency divided by N
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Functional Description
1.2
12 Externally Driven frefExternal = 12 to 26 MHz TA = 25C
DATA CLOCK START-UP TIME (ms)
DATA CLOCK START-UP TIME (ms)
1.0 0.8 0.6 0.4 0.2 0
11 10 9.0 8.0 7.0 6.0
See Figure 42, TA = 25C frefExternal = 13 MHz Crystal frefInternal = 20 kHz
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0
1.0
2.0
3.0
4.0
5.0
frefInternal (MHz)
CAPACITOR RATIO (C5/C8)
Figure 21. Data Clock Start-up Time versus frefInternal
Figure 22. Data Clock Start-up Time versus Capacitor Ratio for Crystal Reference
4.23 Main Synthesizer Operation
The internal local oscillator (LO) of the MC13180 is derived from the external reference frequency by means of a 3-accumulator, fractional-N synthesizer. The external low pass filter (C7/R4 of Figure 3) has a corner frequency of approximately 140 kHz. fdev is the nominal transmit ROM frequency deviation (typically 157500 Hz). I is the integer portion of the fractional synthesizer R is the numerator portion of the fractional synthesizer frefExternal is the external reference frequency LO is the desired local oscillator frequency then, I = INT (LO/frefExternal - fdev/frefExternal) - 3 R = REM(LO/frefExternal - fdev/frefExternal) x 216 where the INT function is the integer portion of the result and REM is the remainder portion of the result. For Example: fdev = 157500 Hz LO = 2.441 GHz frefExternal = 13 MHz then, I = INT(2.441 GHz/13 MHz - 157.5 kHz/13 MHz) - 3 = 18410 R = REM(2.441GHz/13 MHz - 157.5 kHz/13 MHz) x 216 = 4961810 Accuracy to at least 10 decimal places is suggested.
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MC13180 Product Preview
MOTOROLA
Functional Description
4.24 Transmit ROM Operation
The MC13180 uses a look-up table (LUT or Transmit ROM) to shape incoming transmit data bits and produce a Gaussian filtered mask with BT=0.5. The value of the current data bit, along with knowledge of the previous two bits, determines a unique trajectory for shaping. Only four unique trajectories are required to implement this filter and due to the symmetrical nature of the Gaussian response, these trajectories can be reduced to a single quadrant. Furthermore, without compromising accuracy, this table can be reduced to only 11 values. The output of the LUT is fed to the accumulators of the fractional synthesizer. The seven MSBs are eventually fed to the second port of the main VCO during transmit operation (see Figure 23). For receive operation, the output of the LUT is constantly held to the value contained in R1C1. These 11 trajectory constants are listed in Table 17 (see also Figure 4, Register Map). The actual value to place in the LUT is calculated as: LUT RxCxb10 = (fdev/frefExternal) x 216 x (RxCx constant) This number is then rounded and converted to binary: LUT RxCxb2 = INT((LUT RxCxb10+2)/4) where the INT function is the integer portion of the result. As an example for calculating the LUT value for R4C2 and frefExternal = 13 MHz: LUT R4C2b10 = (157.5kHz/13.0MHz) x 216 x 0.5229292198 = 415.2 LUT R4C2b2 = INT((415.2+2)/4) b10 = INT(104.3) b10 = 104 b10 or 011010000 b2 or 68b16 Table 19 lists all values of RxCx for supported reference frequencies.
Table 17. LUT RxCx Constants
R1C1 R2C2 R2C3 R2C4 R3C1 R3C2 R3C3 R3C4 R4C2 R4C3 R4C4 0.9999739537 0.9980246857 0.9911665663 0.9678427310 0.1881990082 0.5249014674 0.7660791186 0.9043672052 0.5229292198 0.7572459756 0.8722099597
4.25 M-Dual Port Multiplier and B-Dual Port Multiplier
For proper operation of the dual-port synthesizer, it is necessary to maintain a constant deviation injection at the input of Port 2 of the VCO. As can be seen from the Transmit ROM operation and Figure 23, the output of the LUT is fed to a digital multiplier prior to being presented to the input of the modulation DAC. Since the LUT values decrease proportionately with input reference frequency, the multiplier must scale
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MC13180 Product Preview
35
Functional Description
these values to achieve a constant deviation. This scaling is linear. Two programmable constants are used to form the equation of a line, the M & B dual-port multipliers. M-Dual Port Digital Multiplier Value (R17/ 15-8), determines the slope, and B-Dual Port Digital Multiplier Value (R8/7-0), determines the intercept. M-Dual Port Digital Multiplier = (frefExternal) /13MHz * 10810 B-Dual Port Digital Multiplier = (frefExternal) /13MHz * 10010 Table 19 contains slope and intercept point values across all supported input reference frequencies.
4.26 Dual-Port Programmable Delay (R7/15-11)
Just as it is necessary to maintain a constant deviation at Port2 of the VCO, it is also necessary to maintain a constant phase at the FV and FR inputs of the main charge pump. The total delay from the output of the LUT to the FV input of the charge pump is given as: LUT FV delay = 10.5 / (frefExternal) Likewise, the total delay from the LUT to the FR input of the charge pump is: LUT FR delay = 28 ns + Delay where delay is the programmed delay value shown in Table 18. Therefore, for a given external reference frequency: Delay = 10.5 / (frefExternal) - 28 ns. Consult Table 18 for the closest available value. Table 19 lists all values of the programmable delay for supported reference frequencies.
Table 18. Dual-Port Programmable Delay Values
R7/15-11 (decimal) 4 5 6 7 8 9 10 11 12 Delayb10 (ns) 167 208 250 292 333 375 417 458 500 R7/15-11 (decimal) 13 14 15 16 17 18 19 20 21 Delayb10 (ns) 542 583 625 667 708 750 792 833 875
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MC13180 Product Preview
MOTOROLA
37 Table 19. Register Settings and Component Values versus Reference Frequency (all register setting values in hex notation)
Fref= 12MHz 258 28A 2D0 2FB 348 3C1 3CC 3D8 3E2 Fref= 13MHz Fref= 14.40MHz Fref= 15.26MHz Fref= 16.80MHz Fref= 19.22MHz Fref= 19.44MHz Fref= 19.68MHz Fref= 19.88MHz 4B0 D7 D7 D5 D0 28 71 A5 C2 70 A3 BC 64 6C 78 7F AD 9C 93 96 88 80 68 5E 58 50 74 86 8C B4 A2 99 8B 98 89 82 76 68 5E 59 51 46 67 79 46 66 75 A0 25 22 20 1D 19 C0 AD A4 95 82 80 19 46 66 78 45 65 74 A2 C5 B2 A8 98 85 84 C6 B3 A9 99 86 84 C6 B3 A9 9A 86 85 83 83 82 7F 19 45 64 77 45 63 72 A3 4B0 4B0 4B0 4B0 4B0 4B0 4B0 4B0 82 82 81 7E 18 44 63 75 44 62 71 A5 258 63 63 62 60 12 34 4C 5A 34 4B 56 D8 56 64 6E 75 81 94 96 97 99 C8 14 13 11 10 E C C C C 9
Register
Fref= 26MHz 28A
Data Clk R (R6/9-0)
Data Clk N (R7/10-0)
R1C1 (R12/7-0)
R2C2 (R12/15-8)
R2C3 (R13/7-0)
R2C4 (R13/15-8)
R3C1 (R14/7-0)
R3C2 (R14/15-8)
R3C3 (R15/7-0)
MC13180 Product Preview
R3C4 (R15/15-8)
R4C2 (R16/7-0)
R4C3 (R16/15-8)
R4C4 (R17/7-0)
M-Dual Port Multiplier (R17/15-8)
B-Dual Port Multiplier (R8/7-0)
MOTOROLA
Dual Port Programmable Delay (R7/15-11)
38
27 270 0 0 0 0 0 4.7 4.7 4.7 270 270 330 330 390 390 390 390 4.7 27 24 22 20 18 18 18 18 13 10
Table 19. Register Settings and Component Values versus Reference Frequency (Continued) (all register setting values in hex notation)
R4 (k)
C7 (pF)
560
C6 (pF)
MC13180 Product Preview
MOTOROLA
39
VCC C7 Frac-N Metastability Charge Pump FOut FV CPOut Internal Low Pass Filter TXData[0..7] ROMData[0..7] SUMRData[2..9] LOIn R4 VCO Flo Port1 Port2 Trim[0..5] N[0..7] R[0..15] FR Multiplier CLK TXData[0..7] Compensation[0..5] CLK En MULData[0..7] MULData[0..7] DELData[1..7] Delay MOD DAC D[0..6] Vout LPF Vin Vout Flo C6 External Low Pass Filter CLK1 CLK2
TX ROM
8MHz
CLK
TXData[0..7]
FRef
N[0..7]
MC13180 Product Preview Figure 23. Main PLL Synthesizer Block Diagram
R[0..15]
Transmit
VCO Trim[0..5]
MOTOROLA
Functional Description
4.27 Receiver
The MC13180 receiver is intended to be used in Time Division Duplex (TDD), Frequency Hopping Spread Spectrum (FHSS) applications such as Bluetooth. The receiver uses a low intermediate frequency (IF) of 6.0 MHz, and is capable of receiving up to 1.0 Mbit/s Gaussian Frequency Shift Keyed (GFSK) serial data through the entire 2.4 GHz Industrial, Scientific and Medical (ISM) band. The output of the receiver is a demodulated, serial bit stream of 24 Mbit/s data. This data represents a 4X over sample by a 6-bit D/A of the actual demodulated analog data recovered from the desired channel. A detailed discussion of each of the functional blocks within the receiver follows.
4.28 LNA
The first portion of the receiver chain is the Low Noise Amplifier (LNA). The LNA is a bipolar cascode design and provides gain with low noise at RF frequencies. The LNA is designed with a single-ended (unbalanced) input and is converted to a differential (balanced) output by means of an on chip, integrated balun. For optimum performance, the LNA input impedance must be matched to the complex conjugate of the source impedance (usually 50 ). The LNA of the MC13180 exhibits two distinctly different impedances depending upon whether the LNA is active or disabled. During a receive cycle, the S11 of the LNA is shown in Table 20.
Table 20. S11 for LNA During Receive
Frequency 2.45 GHz MAG (dB) -4.3 Angle (degree) -138
The LNA can be matched to 50 by a simple capacitor/inductor network as shown in Figure 24.
CBlock Cmatch Lmatch LNA
Figure 24.
When the LNA is disabled or the device is in the Idle or Transmit mode, the impedance of the LNA becomes the value shown in Table 21.
Table 21. S11 for LNA Disabled
Frequency 2.45 GHz MAG (dB) -8.9 Angle (degree) 42
The use of an antenna switch to interface the LNA with an antenna is the preferred circuit configuration as illustrated in Figure 42. In this implementation, a true RF Single-Pole, Double-Throw (SPDT) switch is used to isolate the PA output from the LNA input during receive and transmit modes. A 1/4 wavelength trace is not required. As a result, this implementation has the highest performance (due to the lowest loss) and smallest size at the
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MC13180 Product Preview
MOTOROLA
Functional Description
penalty of increased system cost. An external switch must be used for Class 1 Bluetooth devices as the LNA input will become overloaded if not sufficiently isolated from the external PA output. The LNA provides a nominal 6.7 dB of power gain when properly matched. The LNA is enabled approximately 150 s after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode.
4.29 High/Low Image Reject Mixer (I/R Mixer)
The mixer is used to convert the desired RF channel to a 6.0 MHz Intermediate Frequency (IF). The mixer is completely balanced on all ports, and the local oscillator (LO) is derived from the buffered output of the on-chip Voltage Controlled Oscillator (VCO). In general, it is desired to keep all image frequencies in-band. Therefore, when receiving the 6 lowest channels, the mixer can be programmed for high-side injection and the LO will be programmed to be 6.0 MHz above the desired channel frequency. When receiving the 6 highest channels, the mixer can be programmed for low-side injection and the LO will be programmed to be 6.0 MHz below the desired channel frequency. This is illustrated in Figure 25. Selection of high or low side injection is accomplished by bit R2/11 of the register map. For all other in-band channels, the choice of high or low side injection is arbitrary, although it is recommended to use high-side injection for frequencies to 2.440 GHz and low-side injection thereafter.
LO RF Image
High-side LO injection (R2/11=1) LO Image RF
Low-side LO injection (R2/11 = 0)
Figure 25. High-Side and Low-Side Mixer Injection
The mixer delivers approximately 15.8 dB of voltage gain and 22 dB of image rejection. The mixer is enabled approximately 150 s after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode.
4.30 Post Mixer Amplifier (PMA)
Once the desired RF channel has been down converted to the IF frequency, the PMA is used to deliver 12 dB of additional gain prior to feeding the signal into the bandpass filter. The PMA is enabled approximately 10 s after the assertion of the RTXEN pin when programmed for Receive mode. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode.
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MC13180 Product Preview
41
Functional Description
4.31 Bandpass Filter (BPF)
The 6.0 MHz bandpass filter is used to block undesired channels. The filter is self-adjusting and is calibrated during each receive cycle, based on an internally generated 6.0 MHz signal. The gain of the filter is fixed at 4.0 dB. The nominal pass band for the filter is 720 kHz. This deliberately low pass band can cause significant intersymbol interference (ISI) issues for a GFSK modulated signal with a 1Mbit/s data rate. The advantages are increased sensitivity, adjacent channel interference performance and ease of manufacture. Due to this low pass band, a digitally implemented decoder scheme is utilized to eliminate ISI. This is referenced as the JD/MLSE, and is incorporated into all Motorola Bluetooth basebands. The BPF is enabled approximately 10 s after the assertion of the RTXEN pin while programmed for Receive mode and automatic tuning is complete after approximately 140 s. It is disabled immediately after the de-assertion of the RTXEN pin or during any Idle or Transmit mode.
4.32 Limiter with Received Signal Strength Indicator (RSSI)
The RSSI (received signal strength indicator) is integrated into the limiter. The RSSI ADC converts the RSSI current into a 4-bit digital signal. When the RSSI enable (R4/6) and RSSI Read Enable (R9/8) are both set, the 4-bit RSSI conversion value can be read from the MC13180 register map (R29/3-0) while in Idle mode. The RSSI is updated approximately 40 s after TpropFS during a receive cycle (see Figure 12). Enabling RSSI will result in additional current consumption as noted in the Receiver AC Electrical Specifications. Figure 26 shows the RSSI conversion value versus the RF level input to the LNA at various temperatures. Figure 27 shows the RSSI conversion versus the RF level at different power supplies.
-40 -45
RF LEVEL @ RFIN (dB)
-40
TA = 85C 55C
2.5 and 2.7 V -45
RF LEVEL @ RFIN (dB)
-50 -55 -60 -65 -70 -75 1.0 -20C
25C
-50 3.1 V -55 -60 -65 -70
TA = 25C
0C -40C
3.0
5.0
7.0
9.0
11
13
15
-75 1.0
3.0
5.0
7.0
9.0
11
13
15
RSSI CONVERSION VALUE
RSSI CONVERSION VALUE
Figure 26. RF Level versus RSSI at Temperature
Figure 27. RF Level versus RSSI at VCCRF
4.33 Demodulator
The receiver in the MC13180 downconverts the RF signal and demodulates it. The demodulator takes the IF signal from the limiter and delivers a baseband signal to an A/D converter (ADC). The 6-bit ADC uses the Redundant Sign Digit (RSD) Cyclic architecture that samples the analog input at 4.0 Msamples/s. The resulting demodulated data out of the MC13180 is a 24 Mbit/s, 2's-complement serial bit stream. The start of each 6-bit data stream is indicated by a frame sync (FS) signal. A 24 MHz clock output accompanies the demodulated data.
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MC13180 Product Preview
MOTOROLA
Functional Description
4.34 Receiver Characteristics
For optimum intermodulation and C/I performance, the MC13180 ground flag requires good conduction to the PCB ground layer. Refer to Figure 48 for additional information. Figures 28 through 34 show typical performance of the receiver for various conditions.
-78
CONTINUOUS WAVE INTERFERING SIGNAL POWER LEVEL (dBm)
80 Application Circuit , See Figure 42 60 40 20 0 -20 -40 -60 -80 0 Test Circuit , See Figure 3 1.0 2.0 TA = 25C Power Level Measured for BER < 0.1% Received Frequency = 2.460 GHz 3.0 4.0 5.0 6.0 7.0
-79 -80
SENSITIVITY (dBm)
-81 -82 -83 -84 -85 -86 -87 -88 -20 -5.0 10 25 40 55 70 85
TEMPERATURE (C)
CONTINUOUS WAVE INTERFERING SIGNAL FREQUENCY (GHz)
Figure 28. Receive Sensitivity versus Temperature
10
Figure 29. Blocking Performance versus Continuous Wave Interfering Signal
INTERFERER LEVEL (dBc)
0 -10 -20 -30 -40 -50 -60 -4.0 6.0 16 26 36 46 56 66 76 TA = 25C
INTERFERER FREQUENCY DELTA (MHz)
Figure 30. C/I Performance for Channel 3 (2.405 GHz, High-Side Injection)
10
INTERFERER LEVEL (dBc)
0 -10 -20 -30 -40 -50 -60 -76 -66 -56 -46 -36 -26 -16 -6.0 4.0 TA = 25C
INTERFERER FREQUENCY DELTA (MHz)
Figure 31. C/I Performance for Channel 75 (2.477 GHz, Low-Side Injection)
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MC13180 Product Preview
43
Functional Description
10
INTERFERER LEVEL (dBc)
0 -10 -20 -30 -40 -50 -60 -40 -30 -20 -10 0 10 20 30 40 TA = 25C
INTERFERER FREQUENCY DELTA (MHz)
Figure 32. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection)
10
INTERFERER LEVEL (dBc)
0 -10 -20 -30 -40 -50 -60 -15 -10 -5.0 0 5.0 10 15 TA = 25C
INTERFERER FREQUENCY DELTA (MHz)
Figure 33. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection)
10 0
INTERFERER LEVEL (dBc)
-10 -20 TA = 85C -30 -40 -50 -60 -3.0 -1.0 1.0 -20C 3.0 5.0 7.0 9.0 11 13 15
INTERFERER FREQUENCY DELTA (MHz)
Figure 34. C/I Performance versus Temperature
4.35 Transmitter
The MC13180 uses a direct launch transmitter, taken from the output of the local oscillator (LO). During a transmit cycle the VCO of the LO is automatically trimmed. Following the LO are the output power stages, sequenced in the proper order. To minimize splattering, the output of the programmable low power
44
MC13180 Product Preview
MOTOROLA
Functional Description
amplifier (LPA) drives a balanced ramp up/ramp down generator, which is fed to a "Balun" to provide a single-ended output for the external antenna switch. The transmit start up/warm down sequences are shown in Figure 38.
4.36 Programmable LPA
The output power of the LPA can be varied by programming PA Bias Adjust (R5/2-0) in the register map. Table 22 displays the response of RF output power, current consumption and 2nd Harmonic power level with respect to the programmable bit settings. Class 1 operations are supported through the use of an external power amplifier not shown here. Refer to Applications Information Class 1 Operation for more detail. Figures 35 and 36 provide additional LPA characteristic data.
4.37 Ramp Generator
The ramp generator has an exponential ramp up/ramp down function with a maximum settling time of 20 s. Increasing the output power exponentially is useful to avoid splattering and minimize load pulling.
4.38 External Balun
The LPA provides a differential output that is converted to a single ended signal through the use of an inexpensive printed circuit board balun. Optionally, an external discrete balun may be used. Figures 37 and 42 show the physical dimensions and characteristics of this network. Table 23 shows the output impedance, S22 of the PA during active and inactive cycles.
Table 22. RF Power Out versus PA Bias Adjust
PA Bias Adjust R5/2 0 0 0 0 1 1 1 1 R5/1 0 0 1 1 0 0 1 1 R5/0 0 1 0 1 0 1 0 1 Output Power (dBm) Current Consumption (Continuous Transmit)(mA) 23 20 27 22 33 27 40 35
2nd Harmonic (dBc)
-0.9 -10.8 1.9 -7.6 5.3 -3.5 6.1 3.5
-21 -29 -19 -24 -18 -18 -20 -14
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MC13180 Product Preview
45
Functional Description
3.0 2.5 2.0 1.5 1.0 TA = 25C 0.5 0 2400
2.5 2.0 1.5 1.0 0.5 0 -40 VCCRF = 2.7 V
Pout, OUTPUT POWER (dB)
Pout, OUTPUT POWER (dB)
2420
2440 f, FREQUENCY (MHz)
2460
2480
-15
10
35
60
85
TEMPERATURE (C)
Figure 35. RF Output Power versus Carrier Frequency
Figure 36. RF Output Power versus Temperature
22 81 86 gnd C13 33 pF PAPin 8 TL3 8 32 TL4 PA+ Pin 6 12 C4 3.3 pF gnd Center of QFN Pads 34
MC13180 Balun Substrate r = 3.9 Finished Metal Thickness = 1.7 mils Substrate thickness to ground = 10 mils Units are in mils See Figure 42
44
TL1 C11 1.5 pF TL2
R5 620 R6 620 C12 560 pF Via to Power Plane
19.8
Figure 37. Balun Physical Dimensions Table 23. S22 for PA During Transmit (R5/2-0 = 010)(Measured Differential-Ended)
Operation Mode Active Inactive Frequency (GHz) 2.45 2.45 MAG (dB) -5.5 0.2 Angle (degree) -120 -111
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MC13180 Product Preview
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Functional Description
4.39 External Antenna Switch
An external antenna switch, shown in Figure 42, provides isolation between the PA output and the LNA input, and subsequently enables transmit and receive cycles. The controls to the switch are GPO and EPAEN, Pins 9 and 4, respectively, of the MC13180 device. When GPO is high, the switch is set to transmit mode. EPAEN serves as a complementary driver in this configuration. See Applications Information General Purpose Output and External Power Amplifier for further discussion.
4.40 General Purpose Output (GPO) Pin
The MC13180 General Purpose Output (GPO) is located at Pin 9 of the device. Its output is programmed for general use by setting bit R2/8 in the register map. The GPO can serve as a control line for an external antenna switch.
4.41 External Power Amplifier Enable (EPAEN) Pin
The External Power Amplifier Enable (EPAEN) output of MC13180 is located at Pin 4 of the device. EPAEN may be used in two applications. It may assist in Class 1 Operation by driving an external power amplifier; or it may serve as a complementary driver to a dual port antenna switch as seen in Figure 42. If EPAEN is not required for the desired application, it may be disabled by setting R11/6 to zero.
1.0 s
RTXEN
106 s 15 s
EPADAC (R9/7 = 1) 44 s GPO (Antenna Switch) 1.0 s 15 s
EPAEN (R11/6 = 1)
4.0 s
Internal PA Enable
20 s 5.0 s
20 s
Power Ramp Transmit Sync Delay (R8/15-8 = 18410) 18410
Figure 38. Ramp Generator (Transmit Cycle) Timing Diagram
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MC13180 Product Preview
47
Applications Information
5 Applications Information
5.1 General Purpose Output (GPO)
The GPO must be set to a logic one during a transmit cycle and set to a logic zero during a receive cycle via a SPI write operation, when driving an external antenna switch as shown in Figure 42. When the GPO is not actively used to drive a peripheral, R2/8 in the address register map is considered a don't care.
5.2 General Purpose Output Invert (GPO Invert)
The MC13180 General Purpose Output (GPO) Invert bit (R3/6) can be used to invert the output value of GPO located at Pin 9 of the device. The default setting for GPO Invert is zero (i.e., no inversion). When it is set to one, the GPO output pin assumes the inverted value of GPO in the register map location R2/8. This is a useful feature when an inverter is not available. It can serve as a complement to GPO Invert.
5.3 External Power Amplifier Enable (EPAEN)
The External Power Amplifier Enable (EPAEN) bit, R6/15, can be used in two applications. It may serve as a complementary driver to a dual-port antenna. This is accomplished when External PA Enable Invert, R3/10, is set to a logic one. In this configuration, EPAEN assumes the inverted value of GPO, which is the second driver for the antenna switch. EPAEN may also assist in Class 1 operation by setting bit R11/6 to a logic high. This setting allows the MC13180 to drive an external power amplifer. Setting bits R11/6 and R3/10 to zero disables EPAEN.
5.4 External Power Amplifier DAC (EPADAC)
The Bluetooth specification for Class 1 Power implementation requires power control from 4.0 dBm (or less) to 20 dBm (max) power. The MC13180 external power amplifier digital to analog converter (EPADAC) output (Pin 10) provides a voltage reference for power control of an external power amplifier (PA), if desired. The EPADAC output is enabled when External PA DAC Enable (R11/7) is set to one. Setting R11/7 to zero pulls the EPADAC output to ground. When enabled, the EPADAC output voltage is controlled by the PA DAC setting (R3/5-0). The minimum EPADAC output voltage is 0 Vdc and the maximum output voltage is 3.2 Vdc. The 6-bit resolution of the PA DAC setting corresponds to approximately 50 mV/bit. When using a VCCRF < 3.2 Vdc, the maximum EPADAC output voltage is reduced to VCCRF (i.e., the full-scale output of the PA DAC is referenced to 3.2 V). To obtain optimum functionality of EPADAC with an external PA, this feature should be utilized with the External PA Enable. Refer to the Applications Information section for additional usage information. The output of the EPADAC, when enabled, is gated by the MC13180 sequence manager. During a Sleep, Idle, or RX cycle, the output is set to zero volts. The programmed value of the output voltage is only achieved during an active TX cycle as shown in Figure 38.
5.5 PIN Implementation of Antenna Switch
An alternative approach to using an RF switch is to utilize a PIN diode technique as shown in Figure 39. When both PIN diodes are in the high resistance (i.e., un-biased) state, the transmitter is isolated from the antenna and LNA input. Conversely, when both PIN diodes are in the low resistance (i.e., forward-biased)
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MC13180 Product Preview
MOTOROLA
Applications Information
state, the /4 section appears as an open circuit from the transmitter output to the LNA input, and the transmitter output is coupled directly to the antenna through the bandpass filter. For receive mode, GPO is set low. For transmit mode, GPO is set high. Some advantages to this implementation would be very low current consumption while in receive or idle mode, moderate current consumption while in transmit mode, high receiver isolation, and low cost.
/4
LNA Antenna Pin 1 GPO Pin 9 Band Pass Filter
Pin 6 Balun Pin 8 PA
Figure 39. PIN Implementation of Antenna Switch
5.6 Class 1 Operation
Class 1 Operation can be realized by the MC13180 with the use of an external power amplifier (PA) such as the MRFIC2408 as shown in Figure 40. During a transmit cycle EPAEN drives the external PA Bias Enable. Figure 38 shows the transmitter warm up sequence for this mode of operation. The external PA is required to be fully powered within 5 s. It is recommended that the antenna switch be set to the TX position before the internal PA is enabled. This option minimizes frequency pulling of the VCO, which may appear as splatter. The power level of the external PA can be digitally controlled through the use of a digital-to-analog converter (EPADAC) internal to the MC13180. To access the DAC capability, External PA DAC Enable (R11/7), must be set to one.This line is generally decoupled with a small capacitor value ( 0.1 F). Approximately 44 s is available to fully charge this capacitor (see Figure 38).
5.7 Manufacturer Code
The format of the device identification code is shown in Figure 41. The 32-bit value is defined in the IEEE 1149.1 specification.
MOTOROLA
MC13180 Product Preview
49
Applications Information
System Supply 3.0 V
MRFIC2408
VCC1 RFin
VCC2
RFout
Bias Switch EN VPC
EPAEN RFin (LNA) Printed Balun PA+ PA-
EPADAC
RTXEN
MC13180
NOTE: MC13180 is used at 2.7 V, therefore EPAEN and EPADAC are 2.7 V lines that feed into the MRFIC2408. The MRFIC2408 is specified to operate at 3.0 V or above but is functional at 2.7 V with a slight degradation in performance.
Figure 40.
R31/15-12 Manufacturer Version Number MSB 4 Bits R31/11-0 R30/15-12 R30/11-8 # of continuation code bytes R30/7-1 R30/0
Manufacturer Part Number
Most significant byte (as noncontinuation) code
1 LSB
16 Bits
4 Bits =0
7 Bits
Figure 41. Manufacturer Identification Code
50
MC13180 Product Preview
MOTOROLA
VccLNA
VccMIX
VccMOD
VccPRE
C10 U6 42 48 TL7 5 J1 C16 6.8p V2 J3 TL5 2 3 4 C4 VccPA 6 7 TL2 VccRF 9 10 11 C12 560p 33p TL1 TL3 C13 C11 1.5 p (0.1 pF) 12 TL4 8 PAGPO EPADAC TIN+ TINTOUT+ GNDLIM VCCLIM GNDDEM VCCDEM PA+ GNDPA VCCPA R6 620 3.3p 5 EPAEN GNDLNA RFIN GNDLNA 1 AS179-92 Alpha Industries 6 N/C N/C 1 C9 VCCLNA GNDMIX VCCMIX VCCMOD GNDMOD GNDVCO GND VCCVCO 2 C41 L1 3.9n U7 47 46 45 44 43 41 40 4 V1 J2 GNDPRE 3 TL6 22p 39 38 MLPF VCCPRE 37 GNDCP VCCCP
TOUT-
GNDX
BASE
EMM
COLL
DCVCO
13
15
16
17
14
18
19
20
21
22
23
R5
620
24
DCCP
SMA Johnson 142-0701-881
Murata
TL8
LFSN25N19C2450B FL1
2.4 GHz BPF
VccCP
51
C6 N/C C7 270p R4 27k TP3 VccVCO VSS VDD VDDINT RES CE SDATA 36 35 34 33 32 31 NRES NCEN SPID C37 1.0
Vdd VddINT
MC13180
SCK CLK FS RFDATA RTXEN VCCDC
30 29 28 27 26 25
SPICK CLK FS RFDataIO RTXEN
VccDC
VccXTAL C42 C45 N/C N/C C44 TP4 VccLIM VccDEMO TP1 C43 N/C C5 22p N/C
MC13180 Product Preview
TP2 13 MHz Y1
Printed Transmission Lines TL1 = 77 W, 9.9 @ 2.45 GHz TL2 = 77 , 9.9 @ 2.45 GHz TL3 = 77 , 10.5 @ 2.45 GHz TL4 = 77 , 10.5 @ 2.45 GHz TL5 = 50 TL6 = 50 TL7 = 50 TL8 = 50
Default Units: Microfarads, Microhenries and Ohms N/C = No Component
R2
N/C
R1 0
NDK W-168-179
C8 12p C3 N/C C2 33 n
MOTOROLA
Figure 42. Application Evaluation Schematic (Continued on Page 52)
52
Vcc C38 1 F VccRF VccVCO VccMIX VccMOD VccDC VccPA VccXTAL 6 5 C22 4 C40 470p C39 1.0 VccLIM VccLNA VccRF R11 C18 6.8p 100n C26 N/C VccCP VccDEMO 100n 2.2n 6.8p 100n C23 C24 C28 C31 100n U3 1 VIN GND SHDN ERROR TC1073-2.7VCT713 MicroChip BYPASS VOUT 2 3 R10 N/C VccPRE C29 100n Vdd R12 N/C N/C C25
J2
1
2
3
4
RF DC Pwr
For TC1071VCT Only
NOTE:
J1 I/O Conn.
R10 can be utilized as a regulator bypass. R11, R12, and C25 can be utilized for alternative regulator configurations.
R13 VddINT N/C 1 CLK 5 FS NRES RTXEN NCEN SPICK 7 9 11 13 15 17 VddINT 19 3 2 4 6 8 10 12 14 16 18 20 RFDataIO SPID R14 N/C
MC13180 Product Preview Figure 42 Application Evaluation Schematic (Continued)
MOTOROLA
Application Evaluation Printed Circuit Boards
6 Application Evaluation Printed Circuit Boards
Figure 43. Application Evaluation PCB Assembly Diagram (Not to Scale) Table 24. Application Evaluation PCB Bill of Materials
REF R1 R2, 10, 11, 12, 13, 14 R4 R5, R6 C2 C3, 6, 9, 16, 25, 42, 43, 44, 45 C4 C5, 10 C7 N/C = No Component Size 0402 0402 0402 0402 0402 0402 Value 0 N/C 27 k 620 33 n N/C P27kjct-nd P620kjct-nd PCC2140CT-ND Digikey Digikey Digikey Part Number CR0402-16W-000 Source VENKEL
0402 0402 0402
3.3 p 22 p 270 p
EVK105CH3R3JW C0402COG500220JNE PCC1714CT-ND
TAIYO YUDEN VENKEL Digikey
MOTOROLA
MC13180 Product Preview
53
Application Evaluation Printed Circuit Boards Table 24. Application Evaluation PCB Bill of Materials (Continued)
REF C8 C11 C12 C13 C18, 24, 41 C22, 26, 28, 29, 31 C23 C37, 38, 39 C40 L1 U7 U6 Y1 FL1 U3 (standard) U3 (optional) J1 J2 SMA Size 0402 0402 0402 0402 0402 0402 0402 0603 0402 0402 QFN-48 SC-706 2.5 x 4 mm 2.5 X 3.2 mm SOT-23-6 SOT-23-5 10 X 2 2X1 SMA Value 12 p 1.5 p (0.1 pF) 560 p 33 p 6.8 p 100 n 2.2 n 1.0 470 p 3.9 n Transceiver RF Switch 13 MHz 2.4 GHz 2.7 V Adjustable Socket Connector Connector Part Number PCC120CQCT-ND EVK105CH1R5BW C0402X7R500561JNE C0402COG500330JNE C0402COG5006R8JNE C0402X7R500104JNE PCC222BQCT-ND LMK107F105ZA PCC471BQCT-ND HK1005-3N9S MC13180 AS179-92 W-168-179 LFSN25N19C2450BAHA504 TC1073-2.7VCH713 TC1071VCT 66956-010 22-05-3021 142-0701-881 Source Digikey TAIYO YUDEN VENKEL VENKEL VENKEL VENKEL Digikey TAIYO YUDEN Digikey TAIYO YUDEN Motorola Alpha Indust. NDK Murata Microchip Microchip Newark Newark Johnson
54
MC13180 Product Preview
MOTOROLA
Application Evaluation Printed Circuit Boards
1.120 in
Figure 44. Top Side
1.175 in
Figure 45. Ground Plane
Figure 46. VCC Plane
Figure 47. Bottom Plane
MOTOROLA
MC13180 Product Preview
55
Application Evaluation Printed Circuit Boards
NOTE: Solder Paste: SMQ92J, Indium Corp Solder Stencil Thickness: 5 mils screen Solder Stencil QFN Ground Flag Area: 80% of sodlerable area Solder Stencil QFN Lead Pad Area: 100% of solderable area The ground flag requires good condition for optimum intermodulation and C/I performance.
Figure 48. Recommended QFN Ground Flag Configuration
56
MC13180 Product Preview
MOTOROLA
Packaging
7 Packaging
PIN 1 INDEX AREA
0.1 C A 0.1 C G
2X
7
2X
M 0.1 C 1.0 0.8 1.00 0.75 (0.24) 0.05 0.00 M (0.5) C DETAIL G
VIEW ROTATED 90 CLOCKWISE SEATING PLANE
0.05 C
6
7
B
0.1 C A B 5.25 4.95
37 36 48 1
DETAIL M PIN 1 IDENTIFIER EXPOSED DIE ATTACH PAD
0.25
5.25 4.95 0.1 C A B N
25 24 13
0.5
12
44X
48X
0.5 0.3 VIEW M-M (45)
48X
0.30 0.18 0.1 0.05
M M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. CORNER LEADS CAN BE USED FOR THERMAL OR GROUND AND ARE TIED TO THE DIE ATTACH PAD. THESE LEADS ARE NOT INCLUDED IN THE LEAD COUNT. 6. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 7. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
CAB C
DETAIL T
(90)
(0.25) 0.065 0.015 (2.73)
2X 0.39 0.31
48X
2X
0.1 0.0
DETAIL N
PREFERRED CORNER CONFIGURATION
DETAIL M
PREFERRED PIN 1 BACKSIDE IDENTIFIER
DETAIL T
PREFERRED PIN 1 BACKSIDE IDENTIFIER
4 (45) (90)
DETAIL S
0.60 0.24 (0.4) (0.18) 0.60 0.24 DETAIL N
CORNER CONFIGURATION OPTION 2X
0.39 0.31
0.1 MIN
DETAIL M
PIN 1 BACKSIDE IDENTIFIER OPTION
DETAIL S
PIN 1 BACKSIDE IDENTIFIER OPTION
4
5
Figure 49. Outline Dimensions for QFN-48 (Case 1314-02, Issue C)
MOTOROLA
MC13180 Product Preview
57
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. The Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc., under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002
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